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Director of ASIC Design Engineering

Job Summary:

This is a great opportunity to work with a global team, leading the design and implementation of the next generation Datacenter PCIe/SATA SSD (Solid-State Storage) SoC's.

As a leader of the Storage Research and Design Center SoC development team, you would be responsible for creating an innovative SSD controller design. You will be leading the design team to define and develop Flash Controller H/W architecture(s) and new ASIC design(s) with RTL design & implementation as part of the primary task. You will also work closely with many cross-functional teams in gathering ASIC features requirements and developing a design specification, and then you will also mentor the design team throughout the SoC development phases.

Responsibilities:

  • Managing an SOC design team (including recruiting and building team capabilities)
  • Performing detailed research & analysis of Datacenter PCIe/SATA SSD technologies
    prior to design
  • In charge of driving the development of the SSD Controller ASIC design specification
  • Performing analysis of in-house and 3rd party IP's for SoC integration
  • Driving SoC's physical design implementation with ASIC vendor
  • Working closely with Verification, Validation, and Firmware teams to resolve hardware issues
  • Implementation of SoC design in FPGA prototyping and emulation platforms
  • Investigating/developing the emerging SSD Technologies such as new ECCs (LDPC and BCH), CPUs, Host interfaces, DSP, and high performance protocols
  • Investigation of the Emerging memories such as NAND, MRAM, and RRAM Technologies

Requirements:

Minimum of 10 years of experience in the following domains:

  • Management skills
  • Experience with hiring and retaining people
  • Comfortable with directly managing small (10) to medium (15) sized teams
  • Experienced in SSD controller, SoC architecture, design, and implementation
  • Experienced in SoC implementation, Die/Area size, and Power Estimation
  • Must have experience working with ASIC vendors or internal COT flow for                   physical implementation
  • Must have experience in ASIC Vendor Management (related to package design, SI Analysis, Silicon testing, Characterization, and Qualification)
  • Must have experience working with 3rd party IP vendors
  • Must have experience with Palladium and FPGA Prototyping of complex SoC's
  • Solid experience in PCIe & SATA Host blocks and a firm grasp of the protocol(s)
  • In-depth knowledge of NAND Flash memories & SSD eco-system
  • A proven solid track record in managing & leading a Hardware design team

Education:

  • M.S. EE or Ph.D. in Electrical Engineering or Computer Science

 

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled

 

req # 1564

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