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Principal Firmware Engineer

Toshiba America Electronic Components, Inc.
Location: San Jose, CA


Job Overview:

TAEC is looking for a Principal Firmware Engineer to join its SSD firmware team. In this role, you will work closely with other firmware team members, as well as with cross functional teams including ASIC, hardware, test or application engineering. As a senior team member, you will participate in all phases of the firmware life cycle towards our next generations of SSD products.



Prototyping product concepts and contributing to firmware architecture
Innovation and creativity within the engineering function
Specifying the firmware architecture and developing code targeted for embedded systems
Integrating firmware with other team members for the final product
Assisting test activities (both internal and customer qualifications)
Supporting characterization and benchmarking of SSD products through dedicated firmware instrumentation as necessary.

As a member of the TAEC engineering team, your ideas you will have the opportunity to innovate in a fast growing SSD market



10 years of embedded firmware experience is required, including successfully delivering firmware for two different embedded systems (platforms and CPUs)
Over 10 years in C programming, exposure to C++ a plus.
Strong understanding of RISC processors, including but not limited to: C calling conventions, instruction and data caches, CPU pipeline and its impact to firmware, CPU contexts for interrupts and other operating modes.
5 years of Firmware/System debug skills with tools such as JTAG debugger, GDB and protocol analyzer.
3 years of prior experience with scripting languages for test automation (Perl, Python or similar).
Ability to scope and estimate development effort.
Good oral and written communication skills and ability to work with peer team members.
Proficient and comfortable with standard software development methodologies including source control systems (such as SVN, CVS or similar) and defect tracking systems (such as bugzilla, JIRA or similar)



BS degree required. MS preferred.



Prior SSD design experience with any of the following storage interfaces: SAS, PCIe (NVMe preferred) or SATA.
Development experience of FTL including but not limited to RAID, wear leveling and garbage collection.
Understanding of NAND flash concepts: interfaces (ONFI, Toggle), architectures (MLC, TLC and multiplane) and challenges due to smaller geometries (read and retry)
Experience with Multi-Core firmware design and inter-processor communications.

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