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Principal ASIC Verification Engineern - Validation

Job Summary 

Be a part of a global team to Architect & Develop the next generation of Datacenter PCIe/SATA SSD (Solid-State Storage) SOCs.

As a key member of the Storage Research and Design Center SoC development team, you will be responsible for verifying module designs for the SSD controller. Candidate will be working very closely with verification architects in developing an SV/UVM verification environment. This also includes being responsible for the verification and silicon validation of the module. Throughout the SoC development phase, working closely with design and verification team’s in developing the controller and resolving any hardware issues is a key responsibility for this role.

Responsibilities: 

  • Participate in the SSD Controller ASIC verification methodology and
    environment development
  • Detailed module verification test plan, covering blackbox and whitebox testing
  • Responsible for functional verification of module meeting coverage metrics
  • Work closely with other verification team members in chip level verification
  • Validate SoC design in FPGA prototyping and emulation platforms
  • Work closely with FW engineers to resolve hardware issues
  • Work closely with other verification team members in silicon validation
  • Investigate & participate in the assessment & development of emerging SSD technologies such as new ECCs (LDPC, BCH) CPUs, Host interfaces, DSP & high-performance protocols
  • Participate in continuous improvement of process and methodologies

Requirements: 

Minimum of 7-10 years of experience in the following domains:

  • Strong experience in SSD SoC controller H/W verification
  • Proven experience in developing SV/UVM environments and C-based SoC environments
  • Proven experience in module verification and meeting coverage metrics
  • Experience working with FW engineers in resolving hardware issues
  • Experience working on FPGA prototyping and emulation platforms and debugging
  • Working knowledge of chip level DFT and testing mechanisms

Other:

  • Experience working with storage host protocols is a plus

Education: 

  • BSEE or MSEE in Electrical Engineering or Computer Science

 

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled

 

Req # 1587

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