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Principal ASIC Design Engineer

Candidate will work in Toshiba's exciting global team to Architect & Develop the next generation of Datacenter PCIe/SATA SSD (solid state storage) SOCs.

As a key member of the Storage Research and Design Center SoC development team, candidate will be responsible for developing SoC top level integration and module designs for the SSD controller’s. Candidate will be working very closely with HW and FW architects in developing a design specification, and be responsible for the design, verification and implementation of the module. Throughout the SoC development phase, the candidate will work closely with design and verification team’s in developing the controller and resolving any hardware issues.

Responsibilities: 

  • Participate in the SSD Controller ASIC HW & FW specification development
  • SoC top level integration handling PHY’s, IP’s, IO’s, and clock/reset controls, supporting ASIC, FPGA and Palladium platforms
  • SoC level DFT and test structures for ATE working closely with ASIC Vendor
  • Work with IP vendors on technical due-diligence and integration
  • Detailed module design and functional verification, responsible for physical implementation of module meeting timing
  • Work closely with other design team members in SoC integration and chip level verification and timing
  • Port designs into FPGA prototyping and emulation platforms
  • Work closely with FW engineers to resolve hardware issues
  • Participate in continuous improvement of process and methodologies

Requirements: 

  • Minimum of 7-10 years of experience in the following domains:
  • Strong experience in SSD controller H/W architecture & design
  • Must have worked with IP vendors on technical IP due-diligence, integration and validation
  • SoC integration experience with FPGA and Palladium platforms
  • Proven experience in high performance and low power RTL design of complex modules
  • Proven experience in verifying design with SV/UVM environments
  • Solid experience in synthesis and timing, ability to work with physical implementation team to close timing
  • Working knowledge of chip level DFT, testing mechanisms and test vector development for ATE
  • Experience working with storage host protocols is a plus

 

Education: 

  • BSEE or MSEE in Electrical Engineering or Computer Science

 

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