View Our Website View All Jobs

Director of ASIC Design Engineering

This is a great opportunity to work in Toshiba's global team, leading the design and implementation of next generation Datacenter PCIe/SATA SSD (solid state storage) SoCs.

As a leader of the Storage Research and Design Center SoC development team, the Director, ASIC design is responsible for creating innovative SSD controllers design. The candidate will be leading the design team to define and develop Flash Controller H/W architecture(s) and new ASIC design(s) with RTL design & implementation as part of the primary task. The candidate will work closely with many cross-functional teams in gathering ASIC features requirements and developing a design specification, and then mentor the design team throughout the SoC development phases.

Responsibilities:

  • Manage an SOC design team, including recruiting and building team capabilities
  • Perform detailed research & analysis of Datacenter PCIe/SATA SSD technologies prior to design.
  • Will drive the development of the SSD Controller ASIC design specification.
  • Perform analysis of in-house and 3rd party IP's for SoC integation
  • Drive SoC physical design implementation with ASIC vendor
  • Work closely with Verification, Validation & Firmware teams to resolve hardware issues
  • Implement SoC design in FPGA prototyping and emulation platforms
  • Investigate or develop the emerging SSD technologies such as new ECCs (LDPC, BCH) CPUs, Host interfaces, DSP & high performance protocols.
  • Investigation of the Emerging memories such as NAND, MRAM & RRAM technologies

Requirements:

  • Minimum of 10 years of experience in the following domains:
  • Strong management skills
  • Ability to hire and retain people
  • Comfortable in managing directly small (10) to medium (15) sized teams.
  • Proven experience in SSD controller SoC architecture, design and implementation.
  • Experience in SoC implementation, die/area size & power estimation.
  • Must have experience working with ASIC vendors or internal COT flow for physical implementation
  • Must have experience in ASIC vendor management related to package design, SI analysis, silicon testing, characterization and qualification
  • Must have experience working with 3rd party IP vendors
  • Palladium and FPGA prototyping experience of complex SoC's required.
  • Solid experience in PCIe & SATA Host blocks & understand the protocol(s)
  • In-depth knowledge of NAND Flash memories & SSD eco-system.
  • A proven solid track record in managing & leading a HW design team.

Education:

  • MSEE or PhD in Electrical Engineering or Computer Science
Read More

Apply for this position

Required*
Apply with Indeed
Attach resume as .pdf, .doc, or .docx (limit 2MB) or Paste resume

Paste your resume here or Attach resume file

To comply with government Equal Employment Opportunity / Affirmative Action reporting regulations, we are requesting (but NOT requiring) that you enter this personal data. This information will not be used in connection with any employment decisions, and will be used solely as permitted by state and federal law. Your voluntary cooperation would be appreciated. Learn more.
Gender
Race/Ethnicity
Veteran/Disability status