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Principal ASIC Design Engineer

Job Summary

You will work in a global team using Architecture & Development to make the next generation of Datacenter PCIe/SATA SSD (Solid-State Storage) SOCs. As a key member of the Storage Research and Design Center SoC development team, candidates will be responsible for developing SoC top-level integration and module designs for the SSD controller. The person in this role is also expected to work very closely with HW and FW architects in developing a design specification (this includes being responsible for the design and verification/implementation of the module). Throughout the SoC development phase, the candidate will also work closely with design and verification teams in developing the controller and resolving any hardware issues.

Responsibilities: 

  • Participate in the SSD Controller ASIC HW & FW specification development
  • SoC top-level integration handling PHY’s, IP’s, IO’s, and clock/reset controls, supporting ASIC, FPGA, and Palladium platforms
  • SoC level DFT and test structures for ATE working closely with ASIC Vendor
  • Work with IP vendors on technical due-diligence and integration
  • Detailed module design and functional verification (also responsible for the physical implementation of module meeting timing)
  • Work closely with other design team members in SoC integration and chip-level verification and timing
  • Port designs into FPGA prototyping and emulation platforms
  • Work closely with FW engineers to resolve hardware issues
  • Participate in continuous improvement of process and methodologies

Requirements: 

Minimum of 7-10 years of experience in the following domains:

  • SSD controller H/W architecture & design
  • Must have worked with IP vendors on technical IP due-diligence, integration, and validation
  • SoC integration experience with FPGA and Palladium platforms
  • Proven experience in high performance and low power RTL design of complex modules
  • Experience in verifying design with SV/UVM environments
  • Solid experience in synthesis and timing, ability to work with physical implementation
    team to close timing
  • Working knowledge of chip level DFT, testing mechanisms and test vector
    development for ATE
  • Experience with Storage Host Protocols is a plus

 

Education: 

  • B.S. EE or M.S. EE in Electrical Engineering or Computer Science

 

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled

 

Req # 1588

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