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Principal ASIC Design Engineer - 1759


Candidate will work in Toshiba's exciting global team to Architect & Develop the next generation of Datacenter PCIe/NVMe SSD (solid state storage) SOCs.

As a key member of the Storage Research and Design Center SoC development team, candidate will be responsible for developing module designs for the SSD controllers. Candidate will be working very closely with HW and FW architects in developing a design specification, evaluating in-house and third party IPs, and be responsible for the design, verification and implementation of different SOC modules. Throughout the SoC development phase, the candidate will work closely with design, FW, and verification teams in developing the controller and resolving any hardware, firmware and architectural issues.


  • Participate in the SSD Controller ASIC HW & FW specification development
  • Detailed module design, performance analysis and functional verification
  • Responsible for physical implementation to meet timing requirements
  • Work closely with other SOC team members in SoC integration, chip level verification and timing
  • Port designs into FPGA prototyping and emulation platforms
  • Work closely with FW engineers to resolve hardware issues
  • Investigate & participate in the assessment & development of emerging SSD technologies such as new ECCs (LDPC, BCH), CPUs, Host interfaces, DSP, and high performance storage protocols.
  • Investigate & analyze the landscape of the Silicon storage systems and data access technologies with a good understanding of new features of ever-evolving NVMe and storage standards
  • Investigate controller requirements for emerging memory technologies such as MRAM & ReRAM
  • Participate in continuous improvement of processes and methodologies


Minimum of 10-15 years of experience in the following domains:

  • Strong experience in SSD controller H/W architecture & design
  • Proven experience in high performance and low power RTL design of complex modules
  • Proven experience in verifying design with SV/UVM environments
  • Solid experience in synthesis and timing, ability to work with physical implementation team to close timing
  • Working knowledge of chip level DFT and testing mechanisms
  • Experience working with storage host protocols is a plus


  • BSEE or MSEE in Electrical Engineering or Computer Science

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled

Req # 1759

We are an Equal Opportunity/Affirmative Action Employer including: Minorities/Women/Individuals with Disabilities/Protected

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