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Senior Staff Design Engineer - 3001

Toshiba America Electronic Components, Inc. 
Location: San Jose, CA

Job Description:

As a key member of the mixed signal IP application team for Toshiba America Electronic Components, Inc. (TAEC), the candidate will be responsible for support of Toshiba's multi-protocol high speed interface products. Role will involve working with Tier 1 customers and internal implementation teams to define, integrate and verify high speed interface and other mixed signal IP sub-systems such as but not limited to DDR, PCIe, SATA, Gigabit Ethernet etc. into chips and systems.


  • Work with BU and AE teams during pre-sales to provide more detailed support for the selection and configuration of high speed interface sub-system building blocks and how it impacts the SoC size and power consumption
  • Work with both internal and external Phy and controller development teams during pre-sales to obtain and provide all the necessary collaterals for the whole sub-system  to improve the chances of securing the design win. Collaterals will be, but not limited to all applicable documents and evaluation boards.
  • Work with customers and both internal and external Phy and controller development teams during pre-sales for on-site demonstration and assist customers in their evaluation of Toshiba high speed interface solutions and improve their confidence.
  • Work with both internal and external Phy and controller development teams and AE teams during design implementation to create the sub-system spec. to match customer design requirements, modify verification environment accordingly, run the sub-system verification and then deliver them to customer.
  • Work with both internal and external Phy and controller development and AE teams to successfully integrate and verify the sub-system into customer SoC. This will require assisting customer and implementation teams in RTL verification, timing analysis, RTL and constraint checks, test vector preparation
  • Perform end-2-end SI simulations for high speed interfaces for customer designs using IBIS-AMI models of SerDes and Keysight ADS/Cadence Sigrity
  • Perform other SI (return loss) and PI (self induced supply noise) activities for the high speed interfaces


  • In-depth knowledge high speed interconnect and other mixed signal IP protocols and electrical requirements. Protocols include but not limited to DDR, PCI-Express, SAS, SATA, Interlaken, XAUI, GigE, SDH/SONET, Fiber Channel, Hyper Transport, SFI, SPI, 10G Ethernet, JESD204b, Display Port, HDMI, Vby1
  • Experience in integration and verification of Phy plus controller IPs in customer designs to support the high speed interconnect protocols
  • Experience in providing pre-sales and post-sales application support for Phy and controller IPs
  • Strong experience with Keysight ADS and/or Cadence Sigrity
  • Strong communication and customer interaction skills
  • Ability to develop and/or modify RTL
  • Ability to develop verification test cases using system Verilog
  • Familiarity with design implementation flow and the EDA tool set used in design implementation
  • Familiarity with system level power and signal integrity issues
  • Familiarity with test vector preparation


  • Bachelor’s degree in Engineering (BSEE) required with 10+ years or MSEE with 5+ years.

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled

Req # 3001

We are an Equal Opportunity/Affirmative Action Employer including: Minorities/Women/Individuals with Disabilities/Protected

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